搜索资源列表
adma.tar
- 基于AMBA规范的总线VERILOG HDL 源代码
amba_verilog
- IC设计相关，arm内的AMBA桥实现的源码，verilog语言实现，
AHB_SRRAM
- SSRAM with AHB bus interface source code
I2C
- iic总线挂接在amba的apb总线上，标准接口，verilog代码的实现-iic bus attached to the amba' s apb bus, standard interfaces, verilog code implementation
memc_with_fifo
- Verilog编写的Memory Controller代码，用于AMBA总线下-Verilog code written in Memory Controller
AHBPAPB
- AMBA总线的AHB+APB源程序，供初学者学习。-Verilog for AHB and APB
AMBA_AHB.rar
- amba AHB coding in verilog HDL and integrating with AHB to AXI Brigde,amba AHB coding in verilog HDL and integrating with AHB to AXI Brigde
AHB
- AMBA - AHB MASTER VERILOG CODE (UNCHECKED)
axi_slave
- AMBA axi利用verilog搭建的axi_slave模块-AMBA axi use verilog module built axi_slave
AHBArbiter
- AMBA ahb总线协议的arbiter模块源代码，verilog编写，适合新手学习使用。-this is a code of AMBA AHB arbiter protocol in verilog
APB_slave
- APB slave template for AMBA bus written in Verilog
bus_ahb_to_sram
- amba ahb to sram verilog
abma
- Verilog/VHDL AHB AMBA BUS Arch.
ahb_system_generator_latest.tar
- amba ahb master generator by using verilog
AMBA_VIP
- AMBA 总线IP 核Verilog代码(AMBA bus IP Verilog code)
AMBAaxi
- amba axi specification
axi_slave
- amba总线中axi的slave部分，用verilog实现的slave.(The slave part of Axi in the AMBA bus, slave. implemented with Verilog)
ahb_sram
- amba总线的ahb到sram的接口，Verilog代码，还算详细，算是不错的资料。(The AHB to SRAM interface of the AMBA bus)
AMBA-AXI3-master (1)
- AXI4 verification and design using verilog.